hsmp-381x, 481x surface mount rf pin low distortion attenuator diodes data sheet features diodes optimized for: C low distortion attenuating C microwave frequency operation surface mount packages C single and dual versions C tape and reel options available low failure in time (fit) rate [1] lead free note: 1. for more information see the surface mount pin reliability data sheet. package lead code identi?cation, sot-23 (top view) description/applications the hsmp-381x series is speci?cally designed for low dis- tortion attenuator applications. the hsmp-481x products feature ultra low parasitic inductance in the sot-23 and sot-323 packages. they are speci?cally designed for use at frequencies which are much higher than the upper limit for conventional diodes. a spice model is not available for pin diodes as spice does not provide for a key pin diode characteristic, carrier lifetime. common cathode #4 common anode #3 series #2 single #0 12 3 12 3 12 3 12 3 4810 12 3 dual cathode reverse series #5 12 3 package lead code identi?cation, sot-323 (top view) common cathode f common anode e series c single b 481b dual cathode
2 absolute maximum ratings [1] t c = +25c symbol parameter unit sot-23 sot-323 i f forward current (1 s pulse) amp 1 1 p iv peak inverse voltage v same as v br same as v br t j junction temperature c 150 150 t stg storage temperature c -65 to 150 -65 to 150 jc thermal resistance [2] c/w 500 150 notes: 1. operation in excess of any one of these conditions may result in permanent damage to the device. 2. t c = +25c, where t c is de?ned to be the temperature at the package pins where contact is made to the circuit board. electrical speci?cations t c = +25c (each diode) conventional diodes part number hsmp- package marking code lead code con?guration minimum breakdown voltage v br (v) maximum total capacitance c t (pf) minimum resistance at i f = 0.01ma, rh () maximum resistance at i f = 20ma, r l () maximum resistance at i f = 100ma, rt () resistance at i f = 1ma, r m () 3810 e0 0 single 100 0.35 1500 10 3.0 48 to 70 3812 e2 2 series 3813 e3 3 common anode 3814 e4 4 common cathode 3815 e5 5 reverse series 381b e0 b single 381c e2 c series 381e e3 e common anode 381f e4 f common cathode test conditions v r = v br measure i r 10ua v r = 50v f = 1mhz i f = 0.01ma f = 100mhz i f = 20ma f = 100mhz i f = 100ma f = 100mhz i f = 1ma f = 100mhz high frequency (low inductance, 500 mhz C 3 ghz) pin diodes part number hsmp- package marking code lead code con?guration minimum breakdown voltage v br (v) maximum series resistance r s () series resistance i f = 1ma, r m () typical total capacitance c t (pf) maximum total capacitance c t (pf) typical total inductance l t (nh) 4810 eb b dual cathode 100 3 48 - 70 0.35 0.4 1 481b eb b dual cathode test conditions v r = v br measure i r 10a i f = 100ma f = 100mhz i f = 1ma f = 100mhz v r = 50v f = 1mhz v r = 50v f = 1mhz f = 500mhz - 3ghz
3 typical parameters at t c = 25c part number series resistance carrier lifetime reverse recovery time total capacitance hsmp- r s () (ns) t rr (ns) c t (pf) 381x 53 1500 300 0.27 @ 50 v test conditions i f = 1 ma f = 100 mhz i f = 50 ma i r = 250 ma v r = 10 v i f = 20 ma 90% recovery f = 1 mhz typical parameters at t c = 25c (unless otherwise noted), single diode 10000 1000 100 10 1 rf resistance (ohms) 0.01 0.1 1 10 100 i f C forward bias current (ma) t a = +85 c t a = +25 c t a = C55 c figure 2. rf resistance vs. forward bias current, f = 100mhz 0.15 0.30 0.25 0.20 0.35 0.40 0.45 02 6 41012 816 14 18 20 total capacitance (pf) reverse voltage (v) figure 1. rf capacitance vs. reverse bias. 1 mhz 30 mhz frequency>100 mhz 120 110 100 90 80 70 60 50 40 1000 100 10 diode mounted as a series attenuator in a 50 ohm microstrip and tested at 123 mhz diode rf resistance (ohms) figure 3. 2nd harmonic input intercept point vs. diode rf resistance. input intercept point (dbm) 100 10 1 0.1 0.01 0 0.2 0.4 0.6 0.8 1.0 1.2 i f C forward current (ma) v f C forward voltage (ma) figure 4. forward current vs. forward voltage. 125 c 25 c C50 c input rf in/out figure 5. four diode attenuator. see application note 1048 for details. fixed bias voltage variable bias typical applications for multiple diode products notes: 3. typical values were derived using limited samples during initial produc t characterization and may not be representative of t he overall distribution.
4 microstrip series connection for hsmp-481x series in order to take full advantage of the low inductance of the hsmp-481x series when using them in series applications, both lead 1 and lead 2 should be connected together, as shown in figure 7. microstrip shunt connections for hsmp-481x series in figure 8, the center conductor of the microstrip line is interrupted and leads 1 and 2 of the hsmp-481x series diode are placed across the resulting gap. this forces the 1.5 nh lead inductance of leads 1 and 2 to appear as part of a low pass ?lter, reducing the shunt parasitic inductance and increasing the maximum available attenuation. the 0.3 nhof shunt inductance external to the diode is created by the via holes, and is a good estimate for 0.032" thick material. typical applications for hsmp-481x low inductance series 12 3 hsmp-481x figure 6. internal connections. figure 7. circuit layout. figure 8. circuit layout. figure 9. equivalent circuit. 50 ohm microstrip lines pad connected to ground by two via holes 0.3 nh 0.3 nh 0.3 pf r j 1.5 nh 1.5 nh r j 0.08 + 2.5 i b 0.9
5 typical applications for hsmp-481x low inductance series (continued) co-planar waveguid e groundplane center conductor groundplane 0.3 pf 0.75 nh r j equivalent circuit model hsmp-381x chip* co-planar waveguide shunt connection for hsmp-481x series co-planar waveguide, with ground on the top side of the printed circuit board, is shown in figure 10. since it elimi- nates the need for via holes to ground, it o?ers lower shunt parasitic inductance and higher maximum attenuation when compared to microstrip circuit. figure 10. circuit layout. figure 11. equivalent circuit. 0.18 pf* * measured at -20 v 2.5 r j r s c j r t = 2.5 + r j c t = c p + c j i = forward bias current in ma *see an1124 for package models. r j = 80 i 0.9
6 assembly information sot-323 pcb footprint a recommended pcb pad layout for the miniature sot-323 (sc-70) package is shown in figure 12 (dimensions are in inches). this layout provides ample allowance for package placement by automated assembly equipment without adding parasitics that could impair the performance. smt assembly reliable assembly of surface mount components is a complex process that involves many material, process, and equipment factors, including: method of heating (e.g., ir or vapor phase re?ow, wave soldering, etc.) circuit board material, conductor thickness and pattern, type of solder alloy, and the thermal conductivity and thermal mass of components. components with a low mass, such as the sot-323/-23 package, will reach solder re?ow tempera- tures faster than those with a greater mass. after ramping up from room temperature, the circuit board with components attached to it (held in place with solder paste) passes through one or more preheat zones. the preheat zones increase the temperature of the board and components to prevent thermal shock and begin evaporat- ing solvents from the solder paste. the re?ow zone brie?y elevates the temperature su?ciently to produce a re?ow of the solder. the rates of change of temperature for the ramp-up and cool-down zones are chosen to be low enough to not cause deformation of the board or damage to components due to thermal shock. the maximum temperature in the re?ow zone (t max ) should not exceed 260c. these parameters are typical for a surface mount assembly process for avago diodes. as a general guideline, the circuit board and components should be exposed only to the minimum temperatures and times necessary to achieve a uniform re?ow of solder. 0.026 0.039 0.079 0.022 dimensions in inches 0.039 1 0.039 1 0.079 2.0 0.031 0.8 dimensions in inches mm 0.035 0.9 figure 12. recommended pcb pad layout for avagos sc70 3l/sot-323 products. figure 13. recommended pcb pad layout for avagos sot-23 products. sot-23 pcb footprint
7 package dimensions outline 23 (sot-23) package characteristics lead material .................................................... copper (sot-323); alloy 42 (sot-23) lead finish ......................................................................... tin 100% (lead-free option) maximum soldering temperature ............................................ 260c for 5 seconds minimum lead strength ........................................................................... 2 pounds pull typical package inductance ...................................................................................... 2 nh typical package capacitance ..............................................0.08 pf (opposite leads) outline sot-323 (sc-70) option descriptions -blkg = bulk, 100 pcs. per antistatic bag -tr1g = tape and reel, 3000 devices per 7" reel -tr2g = tape and reel, 10,000 devices per 13" reel tape and reeling conforms to electronic industries rs-481, taping of surface mounted components for automated placement. ordering information specify part number followed by option. for example: hsmp - 381x - xxx bulk or tape and reel option part number; x = lead code surface mount pin e b e2 e 1 e 1 c e xxx l d a a 1 no t es: xxx- package marking drawings are no t t o sca l e d i mens i ons (mm) m i n. 0.79 0.000 0.30 0.08 2.73 1 . 1 5 0.89 1 .78 0.45 2. 1 0 0.45 ma x . 1 .20 0. 1 00 0.54 0.20 3. 1 3 1 .50 1 .02 2.04 0.60 2.70 0.69 s y mbol a a 1 b c d e 1 e e 1 e2 e l e b e 1 e 1 c e xxx l d a a 1 no t es: xxx- package marking drawings are no t t o sca l e d i mens i ons (mm) m i n. 0.80 0.00 0. 1 5 0.08 1 .80 1 . 1 0 1 .80 0.26 ma x . 1 .00 0. 1 0 0.40 0.25 2.25 1 .40 2.40 0.46 s y mbol a a 1 b c d e 1 e e 1 e l 1 .30 t ypica l 0.65 t ypica l
8 note: "ab" represents package marking code. "c" represents date code. end view 8 mm 4 mm top view abc abc abc abc user feed direction cover tape carrier tape reel 9 max a 0 p p 0 d p 2 e f w d 1 ko 8 max b 0 13.5 max t1 description symbol size (mm) size (inches) length width depth pitch bottom hole diameter a 0 b 0 k 0 p d 1 3.15 0.10 2.77 0.10 1.22 0.10 4.00 0.10 1.00 + 0.05 0.124 0.004 0.109 0.004 0.048 0.004 0.157 0.004 0.039 0.002 cavity diameter pitch position d p 0 e 1.50 + 0.10 4.00 0.10 1.75 0.10 0.059 + 0.004 0.157 0.004 0.069 0.004 perforation width thickness w t1 8.00 + 0.30 - 0.10 0.229 0.013 0.315 + 0.012 - 0.004 0.009 0.0005 carrier tape cavity to perforation (width direction) cavity to perforation (length direction) f p 2 3.50 0.05 2.00 0.05 0.138 0.002 0.079 0.002 distance between centerline tape dimensions and product orientation for outline sot-23 device orientation for outlines sot-23/323
tape dimensions and product orientation for outline sot-323 for product information and a complete list of distributors, please go to our web site: www.avagotech.com avago, avago technologies, and the a logo are trademarks of avago technologies in the united states and other countries. data subject to change. copyright ? 2005-2009 avago technologies. all rights reserved. obsoletes av01-0378en av02-0402en - december 22, 2009 p p 0 p 2 f w c d 1 d e a 0 an t 1 (carrier tape thickness) t t (cover tape thickness) an b 0 k 0 description symbol size (mm) size (inches) length width depth pitch bottom hole diameter a 0 b 0 k 0 p d 1 2.40 0.10 2.40 0.10 1.20 0.10 4.00 0.10 1.00 + 0.25 0.094 0.004 0.094 0.004 0.047 0.004 0.157 0.004 0.039 + 0.010 cavity diameter pitch position d p 0 e 1.55 0.05 4.00 0.10 1.75 0.10 0.061 0.002 0.157 0.004 0.069 0.004 perforation width thickness w t 1 8.00 0.30 0.254 0.02 0.315 0.012 0.0100 0.0008 carrier tape cavity to perforation (width direction) cavity to perforation (length direction) f p 2 3.50 0.05 2.00 0.05 0.138 0.002 0.079 0.002 distance for sot-323 (sc70-3 lead) an 8 c max for sot-363 (sc70-6 lead) 10 c max angle width tape thickness c t t 5.4 0.10 0.062 0.001 0.205 0.004 0.0025 0.00004 cover tape
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